1. Field of the Invention
The present invention generally relates to digital logic power supply circuits and, more particularly, to a simple circuit than can be used in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) to supply safe logic zero and logic one signals to hardwired inputs.
2. Description of the Prior Art
In a CMOS IC, it is dangerous to connect a power line, either drain voltage V.sub.dd or source voltage V.sub.ss, to the gate of a positive channel metal oxide silicon (PMOS) or negative channel metal oxide silicon (NMOS) field effect transistor FET). This is because the gate of the transistor is more vulnerable to noise than either the drain or source of the transistor. A noise spike on the gate can break down the gate oxide, causing permanent failure of the device. This leads to a long term reliability problem, especially in noisy environments. The V.sub.dd and V.sub.ss lines can be particularly noisy because they have no noise protection at the pads where they are brought into the IC, and because they tend to pick up noise from the environment outside the IC.
It is typical in digital CMOS circuits to assign the voltages V.sub.dd and V.sub.ss to the logic values logic one and logic zero, respectively. Without loss of generality, it will be assumed in the discussion which follows that this convention is followed; that is, voltage V.sub.dd is assigned to logic one and voltage V.sub.ss is assigned to logic zero.
In many cases, it is necessary to hardwire a circuit input to either logic zero or logic one. This is especially true in very large-scale integrated (VLSI) circuit designs, where a standard module may be used several times in places where its full functionality is not required and some of its inputs require constant logic values. If these hardwired connections are made directly to the V.sub.dd or V.sub.ss lines, it is a difficult and awkward design constraint to ensure that no transistor gate is connected to voltages V.sub.dd or V.sub.ss. It is simpler to provide safe logic zero and logic one level signals which can be used for hardwired inputs.
In most CMOS circuit designs, the reliability problem caused by connecting hardwired inputs to voltages V.sub.dd or V.sub.ss has not been considered. Where there has been an effort to isolate logic zero and logic one signals from the V.sub.dd and V.sub.ss lines, the circuit used to supply these signals is itself often vulnerable to noise on the V.sub.dd or V.sub.ss lines, as there is a transistor gate connected to one of these lines. Moreover, these circuits are typically quite complex, taking up valuable area on the IC.